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- R. F. ARCHER June 18, 1963 COMPOUND CASCADE TRANSISTOR MEMORY CIRCUIT DRIVER Filed Feb. 8, 1960 2 sheetssheet 1 TEM R. F., ARCHER.

.luneA 18, 1963 COMPOUND CA'SCA'DE. TRNSISTIORA MEMORY CIRCUIT DRIVER 2, Sheets-Sheet 2'.

Filed'. Feb. 8, 1960V FIGA R R RA m OF. T T A mmf NE H IB United States Patent O s 094 ss? coMPoUNn cAscAnE rRANsrsroR MEMORY cincuir nnrvnn 'I'he present invention relates generally to coincident current types of magnetic memory systems and, more particularly, is directed to a novel circuit arrangement for providing driving currents therefor.

Typical coincident current memory systems which utilize, in a well known manner, magnetic elements in the form `of toroidal-shaped cores having substantially rectangular-shaped hysteresis loop characteristics have pre- -viously 'been described in articles by J. W. Forrester, entitled Digital Information Storage in Three Dimensions Using7 Magnetic Cores, Journal of Applied Physics, volume 22, pages 44 to 48, January 1951; by Jan A. Rajchman entitled Static Magnetic Matrix Memory and Switching Circuits, RCA Review, volume 13, pages 183 to 201, June 1952; and by Jan A. Rajchman entitled A Myriabit -Magnetic Core Matrix Memory, Oct-ober l1953 `Proceedings of the IRE, pages 1407 to 1421.

With respect to a matrix of magnetic elements which are each selectively employed for storage of binary information, as represented by the relatively stable states of magnetic remanence obtained by individual elements, it is convenient to consider the elements as being arranged in ordered geometric form for operation in accordance with well-known .coincident current techniques. For example, the magnetic elements are arranged in a plurality of columns and rows and are individually selected by means of a separate coordinate selection or row coil which is inductively coupled to all of the elements of a diierent row, and a second coordinate selection or column coil which is inductively coupled to all of the elements of a different column. In such systems, a coincidence of tWo input signals is generally required to provide a magnetomotive iforce of suiicient magnitude to overcome the magnetic coercive force of any o-ne element. Thus, by applying a current impulse to one coordinate selection coil and a coincident current impulse to a second coordinate selection coil disposed normal thereto, each impulse providing a magnetomotive force less than the coercive force of the storage element, only that particular storage element linked by both of the coordinate selection coils experiences a change in Iits state of magnetic remanence to thereby register the binary information represented by the pair of impulses. Such an operation, las described, is generally employed in storing the desired binary bit of information at a particular row and column address.

In order to interrogate a particular storage element to determine the magnetic state thereof, the two coordinate selection coils inductively coupled thereto are again energized in coincidence but in an opposite sense, thus causing the storage element to be returned to its initial state fof magnetic remanence. However, due to the collapse of the magnetic linx in one direction and the buildup in the opposite direction, a voltage impulse is induced in the sensing coil inductively coupled to all of the storage elements. Consequently, the interrogation procedure thus provides an :output impulse indicative of the particular residual state attained by that particular magnetic element, but at the same time, the information initially stored therein is destroyed. Therefore, if the information is to be repeatedly read out, it is necessary that the information iirst be restored after each reading 3,094,687 Patented June 18, 1963 ice operation, and for this purpose ea-ch read cycle is commonly followed by a write cycle in order to restore the storage element to its state of magnetic remanence prior toA the reading operation. However, if the magnetic condition of the element is in the same direction as -that eiected by interrogation, substantially no voltage is induced in the sensing coil as a result of theV magnetomotive force applied to the element. When the memory organ is to be cleared o-f information, the write cycle is generally disabled such that all of the storage elements are simultaneously lreset to a magnetic datum state, all of which concepts are described fully in each of the above-noted articles.

With the advent of transistor type of semiconductor devices, accompanied by the many well-'known advantages to be derived through their use in electronic circuitry, the present-day trend in computer circuitry ldesign is toward the replacement of conventional vacuum tube circuitry with an equivalent transistorized counterpart. However, due to-rigid manufacturing tolerances imposed upon the drive-current requirements for proper loperation of toroidal-shaped ferrite cores and similar wellknown types of magnetic data storage devices such -as twistors and bit wires, it has been found that transistorized counterparts of conventional vacuum tube types of memory current drivers are generally not capable of operating within such rigid ydrive-current tolerances o-f the magnetic elements utilized in the computer memory as data storage devices.

Therefore, the primary object of the present invention is lto lde-vise a novel transistorized current driver which is capable of operating within the rigid drive-current tolerances necessary for proper operation of presentday magnetic data storage devices.

Another object of the present invention is to devise a new and improved tr-ansistorized cur-rent driver which is readily adaptable =to be utilized in conjunction with substantially -any of the various static types of computer memories.

Still another -obgect of the present invention is to devise a new and improved transistorized current `driver which is of relatively simple circuit -coniiguration and yet is fully capable of maintaining vthe memory drivecurrents within the rigid requirements.

In accordance with the present invention, a new and improved transistorized memory current driver has been devised for use in a memory matrix which utilizes a plurality of magnetic elements arranged in rows and columns, a rst plurality of coordinate selection coils each inductively coupled to all of the elements of a different column, a second plurality of coordinate selection coils each inductively coupled to all the elements of a different row, and a sensing coil inductively coupled to all of the storage elements. Such a current driver comprises a iirst and a second transistor device each having an emitter electrode, acollector electrode, and a base electrode, the emitter electrode of the rst transistor device being serially connected with at least one of the coordinate selection coils and the collector electrodes of the two transistors being connected to a common source of unidirectional operating current and to a source of reference potential through a diode device. Means connecting the emitter electrode of the second transistor device with the base electrode of the irst transistor device are provided such that the iirst transistor device is caused to be conductive each time the second transistor device is rendered conductive, each of the transistor devices normally being biased to a non-conducting state, and means connected to the base electrode of the second transistor device are utilized to selectively render the second transistor device conductive.

aos-1,68*?

selectively rendered operative yat predetermined programmed times and in a predetermined programmed sequence during execution of a reading 'and writing cycle of operation with respect to the computer memory.

Due to the fact that the particular manner in which the just-described memory system is -connected in the cornputer circuitry, and thereafter operated, is not considered pertinent to the present invention, a detailed description thereof is not deemed necessary in order to insure a full yand complete comprehension of the various novel `aspects of the present invention. Briefly, however, if it is assumed that it is desired to store a ten-decimal-digit word in memory address 00, i.e., in the leftmost vertical column of cores, X-write driver 13a and X-grounder 15a are selected via selective energization of input terminals 31a and 32a, respectively. Consequently, a drive current of half-select magnitude is thereafter caused to ow from X-grounder a, thence from right to left via conductor 12a through the topmost row of cores, and thereafter through isolation dio-de 14a to X-write driver 13a. Substantially simultaneously therewith, Y-write .driver 24a and Y-grounder 26a are also selected via selective energization of input terminals 33a and 36a, respectively. As a result, a drive current also of half-select magnitude is thereafter caused to ow from Y-grounder 26a, thence downwardly through the leftmost row of cores via conductor 23a, and thereafter through isolation diode 25a to Y-Write driver 24a.

With additional reference to the simplified graphical representation shown in FIG. 2, it can now be seen that, due to the fact that the half-select X-write current flows from right to left through the particular one of cores 11 which is disposed in the eXtreme upper left-hand corner of the matrix, and, simultaneously therewith, the halfselect Y-write current flows downwardly through the same core, the two magnetomotive forces relating to the two half-select write currents are :additive in the region of the selected core in such a manner as to produce a resultant magnetomotive force which is of greater comparative magnitude than the coercive force of the core; consequently, that particular core is magnetically saturated in a counter-clockwise direction :as illustrated 'by the .direction of the arrow. Due to the fact that each of the remaining cores of the topmost row and leftmost column has been subjected to but a single drive current of halfselect magnitude, the magnetic states of all the remaining cores remain unchanged.

After the rst or topmost core in address 00 is thus magnetically 'conditioned representative of, say, a binary 1, X-write driver 13a and X-grounder 15a are both essentially tie-energized and thus rendered ineffective. Thereafter, X-write driver 13b and X-grounder 15b are simultaneously energized if it is desired to cause the next lowerorder core in address 00 to be magnetically conditioned representative of a binary 1; otherwise X-write driver 13b and X-grounder 15b are not so selected, all in essentially the `same manner as just described with respect to the high-order core of address OO. The above-described v sequence 4of events is sequentially repeated until the desired valued word is stored -in address 00, thus completing a writing cycle of operation.

If it is now assumed that it is desired to read out the word now stored in address 00, X-grounder 15a, X-read driver 17a, Y-grounder 26a, and Y-read driver 28a are all essentially selected at the same time by effecting simultaneous energization of corresponding ones of input terminals 32a, 34a, 36a, and 35a. Immediately thereafter, a nr-st half-select drive current is caused to flow upwardly, and a Second half-select drive current is coinl cidentally caused to ilow from left to right through the high-order core of address 00, as diagrammatically illustrated in FIG. 2. Consequently, the high-order core of address O0 is caused to be magnetically saturated in the opposite direction as before; ie., in a clockwise direction. Thus, due to the collapse of the magnetic flux of the selected core in one direction and the build-up in the opposite direction, a voltage impulse is induced in sensing coil 30 indicative of the binary l storage in that particular core. Normally, in response to the voltage impulse induced in sensing coil 30, the two half-select read currents are again reversed, so that the selected core is magnetically saturated in the same direction as before the reading operation was initiated, thus preserving the information initially stored in the selected core; otherwise, the information initially stored therein is not preserved.

In view of the foregoing, it is, of course, obvious that the above-described sequence of events is sequentially repeated until the entire word initially stored in address 00 has been read out and re-stored, if desired.

With reference .to FIG. 3, there is schematically illustrated therein a circuit diagram of a typical memory grounder such as that utilized in various places throughlout the memory system previously shown and described with respect to FIG. 1. More particularly, the grounder comprises a grounded-emitter transistor 37 of the 2N396 variety whose collector electrode is connected to terminal 38. The base electrode of transistor 37 is returned to ground potential by Way of a series-connected network comprising a S479G crystal diode 39 and a 1GO-ohm resistor 40, and is also connected to input terminal 41 through a parallel-connected network comprising a 361()- ohm resistor 42 and a 5010 auf. capacitor 43. The junction of input terminal 41, resistor 42, and capacitor 43 is connected through .a 1K dropping resistor 45 to bias terminal 44, which has a -l-lZ-vol-t ':7%) bias supply (not shown) connected thereto.

The mode of operation of -a grounder of the type illustrated in FIG. 3 is somewhat straightforward. For example, diode 39 is normally conductive due to the positive potential applied to its anode from bias terminal 44. Consequently, a small valued positive potential substantially equal -to the voltage drop across resistor 46 is applied to the base electrode of transistor 37 and thereby causes transistor 37 to be normally non-conductive. As a result, the collector current of transistor 37 is substantially zero, and the impedance between the collector thereof and ground is at a maximum value. However, when the potential at input terminal 41 is selectively caused by the computer control circuitry to become negative Valued, the potential on the base of transistor 37 likewise lbecomes negative valued, and, as a result, transistor 37 is immediately rendered conductive and remains conductive as long as the potential applied to input terminal 41 remains at some negative value. When transistor 37 is thus rendered conductive, the impedance between output terminal 3S and ground is essentially zero. It is therefore evident that terminal 3S is effectively opencircuited whenever the potential at input terminal 41 is essentially of some polarity other than negative; conversely, terminal 38 is effectively short-circuited to ground whenever the potential at input terminal 41 is negative by a magnitude substantially greater than the absolute value of the positive potential applied to the base of transistor 37 from bias terminal 44.

With reference now to FIG. 4, .there is illustrated therein a novel memory current driver constructed in accordance with a preferred embodiment of the present invention. 'Ihe current driver :consists essentially of a 2N396 transistor 47, whose emitter elect-rode is directly connected to terminal 48 and whose collector electrode is connected -to a 4U-volt (Lt-4%) bias supply terminal 49 through a series-connected resistor arrangement comprising a 4-ohm Ll%) wire-wound resistor 50 and a 186- ohm (12%) resistor 51, the junction of resistors 50 and 51 being returned to ground through a 4.7-volt type 1N1519 Zener diode 52. The driver further includes a second transistor 53 of the 2N404 variety whose collector electrode is directly connected to the junction of resistors 50 and 51 and whose emitter electrode is directly connected to the ybase electrode of transistor 47. The emitter electrode of transistor 53 ris also returned ,to ground through a S479G crystai diode 54 and is additionally connecttd to a -l-lZ-volt (i7%) bias terminal 55 through a 2K (i5 resistor 56. The base electrode of transistor 53 is connected to input terminal 57 through a parallelconnected network comprising a 500 auf. (l%) capacitor S8 and a 2K 5%) resistor 59 and is additionally connected to bias terminal 55 through a 15K (15%) resistor 60.

Before describing the mode of operation of the novel memory current driver shown in FIG. 4, it is to be pointed out that a different one of the memory drive or coordinate selection lines threaded through either a row or a column of cores is connected between terminal 48 of a corresponding current driver and terminal 38 of a corresponding current grounder in essentially the same manner as illustrated in FIG. l. Further, for illustrative purposes only and not by way of a limitation, it is assumed that the magnetic data storage elements utilized in the exemplary memory system are toroidal-shaped ferrite cores of the type lat present manufactured by the present assignee as N-400-, each of which at a temperature of 78 degrees Fahrenheit requires a half-select drive current of 200` ma. (i7.5%) through a single-turn conductor threaded through the :aperture thereof. It is further assumed that, eiectively, either an Off triggering potential of from 0 to y 0.3 volts or an On triggering potential of from 7.65 to 8.95 volts is logically applied at all times to input terminal -7 of the current driver by means of the computer control circuitry.

If it is iirst assumed that an Oi triggering potential is applied `to input terminal 57, a small positive potential substantially equal in magnitude to the potential drop across resistor 59 4is lapplied from bias terminal 55 to the base of transistor 53, thus causing transistor 53 to thereafter be in a non-conducting state. As transistor 53 is now considered to be in a non-conducting state such that the emitter current thereof is vsubstantially zero, and as crystal diode 54 is in a conducting state las a result of the positive potential applied to the anode thereof from bias terminal 5S, a small positive potential equal in magnitude to the potential drop across diode 54 is applied from bias terminal 55 to the base of tnansistor 47, thus also rendering transistor 47 non-conductive, so that the emitter current thereof likewise is substantially zero. As long as transistor 47 remains non-conductive, Zener diode 52 maintains a regulated potential substantially equal to 4.5 volts on the collector electrode of transistor 47; otherwise, diode 52 functions essentially as an open circuit. As is well known in the art, a suitable triggering potential is also applied during this time .to input terminal 41 of the current grounder (FIG. 3) such that transistor 437 thereof is rendered non-conductive thereby in the same manner as previously described. Therefore, as the driver and the grounder are both essentially turned Off at this particular moment, substantially no current is allowed to flow through the particular coordinate selection coil connected between terminals 38 and 4S.

It is next assumed that a negative triggering potential is applied to input terminal 41 of the current grounder and is of a magnitude suflicient to forward bias the emitter-base junction of transistor 37 to the extent that the impedance between collector and emitter thereof is reduced substantially to zero, and, substantially coincidentally therewith, an On triggering potential is applied to input terminal 57 of the current driver. As a result of the On triggering potential applied to terminal S7, the emitter-base junction of transistor 53 is forward biased, so that a nominal current of approximately 3.5 ma. is caused to flow outwardly from the base of transistor 53 toward terminal 57 :and is, accordingly, of sufficient magnitude to effect saturation of transistor 53, so that the impedance between collector to emitter thereof is reduced to substantially zero. Upon saturation of transistor 53,

the collector current therefrom is stabilized at a maximum value determined by the values of resistors 51 and 56 plus the collector-to-emi-tter resistance of transistor 53 and fthe magnitudes of the bias potentials applied to terminals 49 and 55. In addition, the potential between emitter and ground of transistor 53 becomes suiiiciently negative to render diode 54 non-conductive and to forward bias the emitter-base junction of transistor 47. Consequently, base current is caused to ow outwardly from transistor 47 of sufficient magnitude to cause saturation thereof. Upon saturation of transistor 47, the collector current is stabilized at a maximum value determined by the values of resistors 50 and 51, the magnitude of the bias potential applied to terminal 49, and the collector-to-emitter resistances of transistors 37 and 47.

As both the current driver and grounder are thus rendered operative in the manner just described, a 200 ma. (i7.5%) half-select drive current is thereafter caused to ilow through the particular coordinate selection line which is connected between terminals 3S and 48; the magnitude of which current, of course, is equal to the magnitude of the emitter current of transistor 47. However, when the current driver and grounder are both rendered inoperative in the manner previously described, the half-select drive current is immediately reduced to zero.

In order that the uniqueness of the just-described current driver may be more fully understood and appreciated, the following description will be directed toward demonstrating the capability of the current driver of maintaining the half-select drive current within the required i7.5% tolerance, which, from ra practical standpoint, has not heretofore been possible with the use of prior current drivers.

First of all, a i4% potential variation at bias terminal 49, due to a change in ambient temperature, component aging, etc., of the power supply connected thereto, reects .a maximum emitter current variation of transistor 47 of ya corresponding l 4%; also, a i2% variation from Ithe nominal value of resistor 51 reflects a maximum emitter current variation of a corresponding 12%. Due to the fact that the value of resistor 5t] is 0f several orders of magnitude smaller than fthe value of resistor 51, the reflected emitter current variation of transistor 47 caused by a maximum deviation of i 1% from the nominal value of resistor S6 is ignored.

It is determined from the manufacturing specifications respecting -a type 2N396 transistor that ythe collector-toemitter potential variation from transistor to tnansfistor, determined during conduction of the transistor, is from .15 to .30 volt and that the potential variation across a conducting DR453 type crystal diode is from .4 to .8 volt from diode to diode of the same type.

It is therefore evident that, during conduction, the summation of the maximum potential Variations across the collector-emitter electrodes of transistors 37 and 47 and the maximum potential variation across the particular isolation diode serially connected between terminals 38 and 4S is .70 volt; i.e., i.875% of the nominal value of the voltage at 'bias terminal 49. Consequently, the maximum reilected emitter current variation from nominal of transistor 47 due to the combined variations from nominal of the values or characteristics of the bias potential at terminal 49, resistors 50 and 5-1, transistors 37 and 47, and the particular isolation diode connected between terminals 38 and 48 is 16.875 which, when subtracted from the i7.5% half-select drive current tolerance, is equal to l.625%.

It is to be appreciated at this point that, due to the fact that the ybase of transistor 47 is directly connected to the emitter of transistor 53, plus the fact that the collecor of transistor `53 is returned to the same bias terminal (49) through the same dropping resistor (51) as the collector of transistor 47, the necessity of maintaining the base current of transistor 47 within a tolerance of :625% is thereby eliminated. This is because substantially all of the base current from transistor 47 is returned to bias terminal 49 via transistor 53 and resistor 51, and, as a result, the summation of the collector and base currents of transistor 47 remains substantially constant.

As previously mentioned, it is assumed lthat the On triggering potential applied to input terminal 57 Varies from 7.65 volts to 18.95 volts due to the tolerances of the logical circuitry connected thereto, which triggering potential variation eiects a 2.52 ma. to 4.15 ma. input current variation at terminal 57. As a result of the 1.63 ma. input current variation at terminal 57, there is reected a m0.4% variation in the emitter current of transistor 47.

Finally, a potential variation of 17% at bias terminal 55 causes a change in the current through resistors 56 and 60, which, over the extreme variation of :L with respect to the value of each of resistors 56 and 60, reects a i0.225 variation in the magnitude of the emitter current of transistor 47.

rIhus, as the summation of all of the various reflected emitter current variations of transistor 47 is equal to i7.5%, it is apparent that the novel current driver, constructed in accordance with the present invention, is fully capable of maintaining the half-select drive current Within the required tolerance of i7.5%. Additionally, such a new and improved current driver is characterized by extreme simplicity of construction and operation and is readily adaptable to be incorporated in substantially any of the various static types of computer memories.

While a particular embodiment of the present invention has been shown and described in detail, it will be obvious to those skilled in the art that changes and modifications may be made without departing from the invention in its broader aspects, and, therefore, the aim in the appended claims is to cover all such changes and modifications as -fall within the true spirit and scope of the invention.

What is claimed is:

1. In a magnetic matrix system including a plurality of magnetic elements arranged in rows and columns, the combination comprising: a .rst plurality of coordinate selection coils each inductively coupled to all of the elements of a different column; a second plurality of coordinate selection coils each inductively coupled to all of the elements of a diierent row; sensing means inductively coupled to all of said elements; a first and a second transistor device each having an emitter electrode, a collector electrode, and a base electrode; means serially connecting the emitter electrode of said rst transistor device with at least one of said coordinate selection coils; means connecting the collector electrode of each of said transistor devices to a common source of unidirectional operating current and to a source of reference potential through a diode device; means connecting the emitter electrode of said second transistor device with the base electrode of said first transistor device such that said first transistor device is caused to be conductive each time said second transistor device is rendered conductive; means to bias each of :said transistor devices to a nonconducting state; and means connected to the base electrode of said second transistor device to selectively render said second transistor device conductive.

2. The combination defined in claim 1 wherein said transistor devices are of like conductivity type.

3. The combination dened in claim l wherein said transistor devices are junction transistors of the PNP variety.

4. The combination defined in claim 1 wherein the emitter electrode of said second transistor device and the base electrode of said rst transistor device are each returned to a source of reference potential through a diode device.

5. The combination dened in claim 1 wherein said diode device is a semiconductor of the Zener type.

References Cited in the le of this patent UNITED STATES PATENTS 2,901,735 Lawrence Aug. 25, 1959 2,914,748 Anderson Nov. 24, 1959 2,929,050 Russell Mar. 15, 1960 2,947,977 Bloch Aug. 2, 1960 2,949,543 Nordahl et al. Aug. 16, 1960 FOREIGN PATENTS 1,186,856 France Mar. 2, 1959 

1. IN A MAGNETIC MATRIX SYSTEM INCLUDING A PLURALITY OF MAGNETIC ELEMENTS ARRANGED IN ROWS AND COLUMNS, THE COMBINATION COMPRISING: A FIRST PLURALITY OF COORDINATE SELECTION COILS EACH INDUCTIVELY COUPLED TO ALL OF THE ELEMENTS OF A DIFFERENT COLUMN; A SECOND PLURALITY OF COORDINATE SELECTION COILS EACH INDUCTIVELY COUPLED TO ALL OF THE ELEMENTS OF A DIFFERENT ROW; SENSING MEANS INDUCTIVELY COUPLED TO ALL OF SAID ELEMENTS; A FIRST AND A SECOND TRANSISTOR DEVICE EACH HAVING AN EMITTER ELECTRODE, A COLLECTOR ELECTRODE, AND A BASE ELECTRODE; MEANS SERIALLY CONNECTING THE EMITTER ELECTRODE OF SAID FIRST TRANSISTOR DEVICE WITH AT LEAST ONE OF SAID COORDINATE SELECTION COILS; MEANS CONNECTING THE COLLECTOR ELECTRODE OF EACH OF SAID TRANSISTOR DEVICES TO A COMMON SOURCE OF UNIDIRECTIONAL OPERATING CURRENT AND TO A SOURCE OF REFERENCE POTENTIAL THROUGH A DIODE DEVICE; MEANS CONNECTING THE EMITTER ELECTRODE OF SAID SECOND TRANSISTOR DEVICE WITH THE BASE ELECTRODE OF SAID FIRST TRANSISTOR DEVICE SUCH THAT SAID FIRST TRANSISTOR DEVICE IS CAUSED TO BE CONDUCTIVE EACH TIME SAID SECOND TRANSISTOR DEVICE IS RENDERED CONDUCTIVE; 